1. Field of the Invention
The present invention relates to a semiconductor memory device and, for example, a semiconductor memory device having, e.g., static memory cells.
2. Description of the Related Art
Along with the advance in the micropatterning technology for semiconductor elements and the improvement of the performance of large-scale integrated circuits (LSIs), high power consumption is becoming a serious problem for recent LSIs. To solve this problem, a technique of dynamically controlling the operating frequency and power supply voltage in accordance with the load of a process is employed. More specifically, in a low-load process, the power consumption is suppressed by reducing the power supply voltage and operating frequency. To reduce the power consumption of an LSI by such control, it is important to minimize the operating voltage in a low-load mode.
However, in a static random access memory (SRAM) that is often used as a semiconductor memory in an LSI, the voltage margin of a memory cell decreases to make it difficult to execute a low-voltage operation as the device scaling progresses. For this reason, an SRAM employs a technique of reducing only the voltage of logic circuit portions without reducing the voltage of the memory cell portion in the LSI. Such an LSI is described in, e.g., Muhammad Khellah et al., “A 4.2-GHz 0.3-mm2 256-Kb Dual-Vcc SRAM Building Block in 65-nm CMOS”, ISSCC Digest of Technical Papers, 2006, pp. 624-625.
In this SRAM, memory cells and word lines connected to them always use a high power supply voltage. Other logic circuit portions, however, use a low voltage when the process load is light. Since a potential difference is produced between the logic power supply and the cell power supply, the row decoder unit of the SRAM requires a level shifter.
The level shifter includes, e.g., a PMOS transistor for pull-up to the cell power supply voltage and an NMOS transistor for pull-down to ground voltage. In the level shifter, the current drivability of the pull-up PMOS transistor needs to be much lower than that of the pull-down NMOS transistor for stable operation. This greatly changes the operation speed between a selected mode and a deselected mode of a word line. Hence, the operation speed of the whole SRAM decreases.